Discussion 13

Instruction Fetch and Control Path

Instruction Fetch

The instruction fetch unit is basically a device that takes the program counter, presents it to the memory as an address, signals a read cycle on the memory, and latches the memory output to the instruction register. In addition it must handle the increment of the PC to get the next instruction, and the addition of a relative jump address for PC relative jumps, or the substitution of a branch address for direct branches.

In the MIPS and other RISC processors, the instruction increment adder has a fixed input (4 if byte addressing, 1 if word addressing). The advantage of knowing this is that a specilized adder can be used -- there is just a single bit input to the second operand, and thus the bit below that point can pass through unaltered and the bits above need only propagate a carry (if necessary).

With a CISC processor, the lengths of instructions vary and so the PC must be incremented by different amounts. This requires that the instruction register be decoded to the point that the length of the instruction can be determined and then that value is passed to the adder. Note, however, that if the instruction spans multiple words, then the fetch unit must cycle that many times to fetch all of the parts of the instruction. It must also fill the appropriate portion of a longer instruction register, and so the control unit must generate an address into the instruction register for each of these cycles.

In a processor such as the 80486, instructions can also be less than a word in length. Thus we might see two instruction in one word, in which case the fetch unit must be able to realign the second instruction once the first is executed (or the control unit must be able to selectively read part of the IR).

In an actual implementation of the Intel architecture, the fetch unit fills a buffer several words long with instructions and it simply watches as the control unit consumes them, refilling the buffer whenever there is a spare memory bus cycle. This gives the control unit more flexible access to the variable width instructions, but also introduces the need for logic to flush the buffer in the event of a branch.

Load and Store

The data load/store unit is similar to the instruction fetch unit in that it provides an interface between memory and register storage. However, it must handle writes in addition to reads.

The data address may come directly from an instruction or be the result of some operation on the instruction and/or the registers. When the address must be computed, it may be generated by a special address arithmetic ALU, or by the same ALU used for normal computation. In the design shown in the book, the latter approach is taken.

What sort of computation is done on addresses? In the case of a relative address, for example, the PC must be added. In a system that does automatic indexing (e.g., incrementing an address automatically), then an increment corresponding to the operand size must be added. Some systems use addressing that is relative to a base address for a process, in which case the address must be added to the base.

A look at the MIPS design shows separate data and instruction memories. This is because the MIPS design uses a cache that is divided between instructions and data. So even though data and instructions are intermixed within main memory, they are in separate memories at the level of the hierarchy closest to the registers. This is a common design approach among many RISC processors now that there is room on the chip for two caches of sufficient size. However, there are still designs that use a "unified" cache, and in this situation the instruction fetch unit and the load/store unit must compete for access to the memory.

The result of an instruction fetch is placed in the instruction register, which is used by the control unit to direct further processing of the instruction. We’ll look at the control unit later. The result of a data fetch is sent to a register. As we saw previously, the loaded data is sent to the register via a multiplexer that selects between the ALU and the output of the memory.

We now have the ability to connect the memory into our system. Next we’ll look at putting that connection together. The remaining piece of the puzzle is how to control the whole thing, and we consider that in just two more classes.

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