Index to Lecture 4

  1. Lecture 4 Outline
  2. Cycles Per Instruction
  3. CPI vs. Clock Rate
  4. Cycles Per Operation
  5. Cycles per operation vs. clock rate
  6. As Technology Progresses...
  7. Limits to Clock Rate
  8. CISC vs. RISC
  9. Why Return to RISC?
  10. Why Did CISC Happen?
  11. Bridging the Semantic Gap
  12. Inflexibility
  13. Benefits of RISC
  14. Intel x86 Architecture (CISC)
  15. Intel Operands/Instructions
  16. Motorola 68000 (CISC)
  17. M68000 more Addressing Modes
  18. M68000 Operands/Instructions
  19. MIPS R4000 family (RISC)
  20. SPARC architecture
  21. PowerPC Architecture
  22. DEC Alpha AXP
  23. HP PA-RISC
  24. Common RISC Features
  25. CISC Features
  26. Optimizing Memory Accesses
  27. Variable Length Instructions
  28. Code Expansion
  29. Explicit vs. Implicit Memory Transfer
  30. Optimization Granularity
  31. Future Paths

 <BACK  INDEX  NEXT>