Index to Lecture 5

  1. Lecture 5 Outline
  2. Impact of Increasing Register Count
  3. Necessary Registers
  4. Sufficient Registers
  5. Evolution of Register Sets
  6. Scalability of General Registers
  7. Inevitable Special Cases
  8. Intel x86 (IA32)
  9. Intel x86 (IA32) MMU
  10. Intel x86 (IA32) Other
  11. Intel Itanium (IA64)
  12. Motorola 680X0
  13. Motorola 680X0 Floating Point
  14. Motorola 680X0 Supervisor
  15. MIPS R4000
  16. HP PA-RISC
  17. DEC Alpha AXP
  18. PowerPC
  19. PowerPC Supervisor
  20. SPARC Register Windows
  21. SPARC Other
  22. Register Windows
  23. Instruction Set Design
  24. Bin-packing
  25. Instruction Types
  26. How many types?
  27. Operating Modes
  28. Decoding/Predecoding

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