Slides From Some Research Presentations
- Compiling for a Moving
Target -- a proposed approach to incorporating configurable computing
hardware into the traditional software compilation process.
- Real-Time RISC Processing
-- RISC processors deliver performance comparable to digital signal processors
in many applications. The unpredictable nature of the timing of their memory
hierarchies makes them difficult to employ in the presence of hard deadlines.
This talk outlines work we are exploring in trying to make RISC architectures
predictable without sacrificing performance.
- Asynchronous SIMD -- Traditional
SIMD arrays suffer from a wide range of fundamental problems that limit
their performance. This talk identifies the major problems and presents
an alternative approach to building an array processor in which the processing
elements operate only in small, locally synchronous groups and interact
asynchronously with elements outside of their local group.
- Heterogeneous Programming in
Java, Gourmet Blend or just a Hill of Beans -- thoughts on using Java
for heterogeneous parallel processing applications. Pros and cons, and
some suggestions for modest changes to the language that would facilitate
this use.
- Meta-Instruction Set Computer
Architectures -- Modern microarchitectures are depending ever more
heavily on compiler support. But at they same time they limit the information
that can be supplied by the compiler in order to preserve the fiction of
a cacheless von Neumann architecture. Even though a modern microarchitecture
may be six-way superscalar, with multiple levels of cache, and sophisticated
prediction and speculation support, the instruction set architecture (ISA)
would have the programmer believe all instructions are fetched from a single
memory and executed with sequential isoation from each other. Through this
restrictive filter, the compiler is expected to statically schedule code
to optimize the use of all the hidden accelleration mechanisms. This talk
explores the effect of slightly shifting the abstraction boundary between
the compiler and the microarchitecture to enable run-time access to all
of the compiler's program dependence information. The result is a meta-instruction
architecture in which compile-time, load-time, and run-time information
can be combined to optimize execution more effectively. As a side benefit,
object code achieves a greater degree of performance portability.